1. Field of the Invention
Generally, the present disclosure relates to integrated circuits including advanced transistor elements, some of which comprise a semiconductor alloy for adjusting transistor characteristics, in particular in the context of sophisticated gate electrode structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface between highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon and/or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid, among other things, the so-called short channel behavior during transistor operation. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although generally usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface separating the gate dielectric from the electrode material, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has also been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the high-k dielectric material within the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also present an additional complex process step, which, however, may avoid complex processes in an advanced stage for adjusting the work function and thus the threshold voltages, as is the case in so-called replacement gate approaches.
Although, in the approach of providing the threshold voltage adjusting semiconductor alloy in an early manufacturing phase, significant yield loss and reduced transistor performance and increased variability of transistor characteristics is observed, in particular in highly scaled transistor elements, which is believed to be at least in part caused by non-uniformities of the threshold voltage adjusting semiconductor alloy in combination with the pronounced surface topography of isolation regions in a transition area between an active region and the isolation structure, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an early manufacturing stage. As illustrated, the device 100 comprises a substrate 101, such as a semiconductor substrate and the like, above which is formed a semiconductor layer 102, which is typically provided in the form of a silicon material. Depending on the device architecture to be implemented in the device 100, the semiconductor layer 102 is directly formed on a crystalline material of the substrate 101 in a bulk configuration, while, in a silicon-on-insulator (SOI) architecture, a buried insulating material (not shown) is formed directly below the semiconductor layer 102. In the manufacturing stage shown, the semiconductor layer 102 is laterally divided into a plurality of active regions 102a, 102b by means of an isolation structure 102c, which is typically provided in the form of a shallow trench isolation. In the example of FIG. 1a, the active region 102a is to be understood as an active region for receiving one or more P-channel transistors, which require an appropriate adaptation of the threshold voltage in combination with a sophisticated high-k metal gate electrode structure, as is discussed above. On the other hand, the active region 102b corresponds to one or more N-channel transistors in which the threshold voltage may be adjusted on the basis of the semiconductor base material and the sophisticated high-k metal gate electrode structure. Consequently, the active region 102a receives a silicon/germanium alloy 103 having an appropriate material composition and a specific layer thickness, as these two parameters significantly determine the finally obtained shift of the threshold voltage. For example, typically a thickness of the material 103 is selected in a range of 6-50 nm, while the germanium content of the layer 103 is selected in the range of approximately 15-30 atomic percent. It turns out, however, that the transistor characteristics significantly depend on a precise adjustment of these parameters, which becomes increasingly difficult when, in particular, the transistor width, indicated by 102w, is reduced in sophisticated transistors, for instance when provided in memory areas of the semiconductor device 100. For example, it has been observed that the thickness of the layer 103 is locally increased at the edge of the active region 102a, as indicated by 103e, thereby forming moderately pronounced elevated portions 103d. On the other hand, the layer thickness in the center of the active region 102a, indicated by 103c, may be significantly reduced compared to the thickness 103e. Consequently, in transistor architectures in which the width 102w is increasingly reduced, the influence of the edge portions 103d increases and may thus result in a pronounced shift of the overall transistor characteristics compared to the target characteristics.
FIG. 1b schematically illustrates the semiconductor device 100 in a situation in which the width 102w is reduced, for instance required in narrow transistors for memory areas so that the fraction of the elevated portions 103d becomes increasingly greater, thereby shifting the threshold voltage characteristics, in particular with respect to other transistors having an increased transistor width. In this case, it is very difficult to target the DC behavior and the AC behavior of the device 100 and thus requires a design which takes into account the pronounced variability in the transistor characteristics due to the thickness variation of the threshold voltage adjusting semiconductor alloy 103.
The semiconductor device 100 as illustrated in FIGS. 1a and 1b may be formed on the basis of the following process strategy. The isolation structure 102c is typically formed by applying well-established lithography, etch, deposition, planarization and anneal techniques in order to form trenches in the semiconductor layer 102 so as to extend to a desired depth and subsequently filling the trenches with an appropriate dielectric material, such as silicon dioxide. Typically, the lithography process is applied so as to provide an appropriate hard mask regime, which may also be used for removing any excess material and obtaining a desired height level of the isolation regions 102c. After the removal of any excess material, one or more appropriate well dopant species are introduced into the active regions 102a, 102b in order to adjust the basic transistor characteristics, thereby using well-established masking regimes and implantation processes. Thereafter, the well dopant species may be activated by performing an anneal process, followed by the deposition of the silicon/germanium alloy 103. To this end, a hard mask material is typically formed on the active region 102b, for instance in the form of a silicon dioxide material, and a selective epitaxial growth process is applied in which process parameters, such as temperature, gas flow rates and the like, are appropriately selected such that a deposition is restricted to exposed crystalline surface areas, while adhesion of material on dielectric surface areas, such as silicon dioxide, is strongly suppressed. During the selective process, appropriate precursor materials, including silicon and germanium, are supplied in a well-controlled manner in order to obtain the desired material composition of the layer 103. Similarly, for given process parameters and thus a given deposition rate, the process time is selected so as to obtain the target layer thickness. Moreover, since generally the epitaxial growth is a complex process step, it is of great importance in volume production process environments to provide superior throughput so that typically so-called batch processes are applied in which a plurality of substrates are commonly processed on the basis of a corresponding batch process tool. For example, the deposition of the layer 103 is typically accomplished in a corresponding process tool in which 25 or significantly more substrates may be processed in a single process step, thereby providing superior overall throughput. However, with reduced feature sizes, increasingly the variability of the layer 103 with respect to layer thickness is observed, as discussed above, which requires superior process recipes, which are currently still under investigation, while, in other cases, it has been proposed to use single substrate process tools in order to establish the selective epitaxial growth ambient. Since any improved process recipes for batch processes are currently not available, with a highly unsure prospective of an availability of such process recipes, and since a process flow based on a single wafer processing requires an enormous increase of the tool resources, there is still room for improving the current situation with respect to providing a threshold voltage adjusting semiconductor alloy selectively for certain transistor types.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, a sophisticated gate electrode structure 160 is formed on the active region 102a comprising the semiconductor alloy 103 and extends above a portion of the isolation region 102c. The gate electrode structure 160 comprises a gate dielectric layer 161 comprising a high-k dielectric material, as discussed above, in order to obtain an acceptable physical thickness and thus an acceptable leakage behavior, while at the same time achieving a desired high capacitive coupling. Moreover, as is also explained above, typically a metal-containing electrode material 162, for instance comprising titanium nitride and the like, is formed on the gate dielectric layer 161, followed by a further electrode material 163, such as a silicon material, a silicon/germanium material and the like. Moreover, in the manufacturing stage shown, a dielectric cap layer or cap layer system 164 may still be present in the gate electrode structure 160. Moreover, since the materials 161, 162 in combination with the layer 103 define the overall transistor characteristics, for instance with respect to threshold voltage and the like, in combination with other transistor characteristics, such as the dopant profile in the active region 102a, any influence on the material characteristics of these materials is to be reduced during the further processing, thereby requiring an efficient encapsulation of the materials 161 and 162, which is typically accomplished by providing an appropriate protective liner or spacer 165, for instance provided in the form of a dense silicon nitride material and the like. For example, the spacer 165 is provided in order to avoid undue chemical interaction with efficient wet chemical recipes which are typically to be applied during the further processing of the device 100.
Upon forming the layer 103 based on the selective epitaxial growth process as discussed above, usually a pronounced surface topography may be created in the isolation region 102c adjacent to the active region 102a so that a certain divot is frequently observed, in particular in the vicinity of active regions having formed therein the threshold voltage adjusting semiconductor alloy 103. Consequently, upon forming the gate electrode structure 160, which requires the deposition and patterning of the materials 161 and 162 in order to provide appropriate work function metal species for different types of transistors, sophisticated patterning conditions may then be encountered upon patterning the layer stack including the layer 163 and 164, which may finally result in patterning related irregularities, in particular at an end portion 160e of the gate electrode structure 160. Moreover, upon depositing and patterning the spacer 165, the pronounced surface topography may also increase the probability of obtaining insufficient coverage of the sensitive materials 161 and 162, which may thus be exposed during the further processing of the device 100.
In order to reduce the overall non-uniformities of the semiconductor alloy 103, various approaches have been proposed, for instance by using an additional masking process when selectively removing a hard mask material from one of the active regions, for instance from the active region 102b (FIG. 1a). In this manner, a high degree of symmetry is obtained with respect to causing material erosion in the isolation region 102c upon forming the alloy 103 selectively in one type of active region. On the other hand, an additional lithography step and corresponding patterning processes are required, thereby also leading to increased overall process complexity. In other approaches, the semiconductor alloy 103 is grown prior to forming the isolation region 102c, as suggested in “Enhancing Uniformity of a Channel Semiconductor Alloy by Forming STI Structures After the Growth Process” by Stephan Kronholz, Martin Trentzsch and Richard Carter in US Patent Publication No. 2010/0289090, the entire disclosure which is herein incorporated by reference. In this application, basically the semiconductor alloy may be formed in an early manufacturing stage on the basis of a global deposition of the alloy, thereby contributing to superior uniformity while, however, not addressing the incorporation of well dopant species with respect to the overall process flow, in particular with respect to the provision of a hard mask material and the performance of a high temperature anneal process in order to activate the well dopant species and reduce implantation-induced damage, for instance, in the semiconductor alloy.
In view of this situation, the present disclosure relates to manufacturing techniques for forming semiconductor devices requiring, in some active regions, the formation of a threshold voltage adjusting semiconductor alloy, while avoiding or at least reducing the effects of one or more of the problems identified above.